Speaker: Edward G. Suh 교수(코넬대학교)
Date & Time: 2019년 7월 15일(월), 10:30
Where: 서울대학교 301동 201호(신공학관)
As shown by Meltdown and Spectre, modern processor architectures are vulnerable to side/covert-channel attacks that exploit hardware-level behaviors not visible in the traditional instruction set architecture (ISA). In particular, timing channels represent one of the most serious threats because they can be exploited in software without physical proximity to a victim system.
This talk will briefly discuss hardware-level side/covert channels in modern computing systems, and show how a processor can be re-designed to provide strong information flow security assurance including protection against microarchitecture-level timing channels. To enable strong protection against timing channels, the talk will discuss how the traditional instruction set architecture can be augmented with a new hardware-software contract for timing behaviors, and how a processor microarchitecture can be re-designed to meet this new contract to control timing channels. Then, the talk will introduce a design methodology based on a secure hardware description language (HDL), which enables designers to statically analyze hardware-level information flow and remove security vulnerabilities including timing channels at design time. Our experiences suggest that the secure HDLs can be used to check security properties of realistic hardware designs with low overhead, while providing strong assurance for timing-safe information flow security. As a concrete example, this talk will discuss our experiences in designing and verifying a new tagged processor architecture, which is prototyped on an open-source RISC-V processor.
G. Edward Suh is a Professor in the School of Electrical and Computer Engineering at Cornell University. He received a Ph.D. degree in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology (MIT) in 2005. Before joining Cornell, he led the commercial development of the Physical Unclonable Function (PUF) technology at Veryao Inc., which is now used in commercial products such as Xilinx UltraScale+ MPSoC for storing secret keys. He also did early research work on dynamic cache partitioning and secure processor technologies, which are widely available in today’s processors. His research interests span computer systems in general with a focus on developing architectural techniques to improve security and efficiency.
※ 7월17일부터 같은 장소에서 Security Architecture와 관련하여 Edward G. Suh 교수님이 다음의 Lecture Series를 진행할 예정입니다.
7/17 (Wed) 10:00am – Basic security concepts
7/19 (Fri) 10:00am – Cryptographic primitives
7/22 (Mon) 10:00am – Secure processors and off-chip memory protection
7/24 (Wed) 10:00am – Microarchitectural timing channels
7/26 (Fri) 10:00am – Physical attacks and hardware security verification
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