Speaker: 박영준 조교수, 한양대학교
Date & Time: 2018년 5월 11일 (금) 15:00
Where: 삼성전자 서울대학교 공동연구소 (관악 연구공원 내) A동 3층 대회의실
Special neural accelerators are an appealing hardware platform for machine learning systems because they provide both high performance and energy efficiency. Although various neural accelerators have recently been introduced, they are difficult to adapt to embedded platforms because current neural accelerators require high memory capacity and bandwidth for the fast preparation of synaptic weights. Embedded platforms are often unable to meet these memory requirements because of their limited resources. In FPGA-based IoT (internet of things) systems, the problem becomes even worse since computation units generated from logic blocks cannot be fully utilized due to the small size of block memory. In order to overcome this problem, we propose a novel dual-track quantization technique to reduce synaptic weight width based on the magnitude of the value while minimizing accuracy loss. In this value-adaptive technique, large and small value weights are quantized differently. In this paper, we present a fully automatic framework called NN Compactor that generates a compact neural accelerator by minimizing the memory requirements of synaptic weights through dual-track quantization and minimizing the logic requirements of PUs with minimum recognition accuracy loss. For the three widely used datasets of MNIST, CNAE-9, and Forest, experimental results demonstrate that our compact neural accelerator achieves an average performance improvement of 6.4x over a baseline embedded system using minimal resources with minimal accuracy loss.
Yongjun Park is an assistant professor in the Division of Computer Science and Engineering at Hanyang University, and his research interest in general is low-power and high performance computer architectures and compilers for mobile devices. Before joining Hanyang University, he was an assistant professor at Hongik University, and a software architect at Intel Corporation, working on software/hardware co-design of future mobile CPUs. He completed his Ph.D. and M.S. at Electrical Engineering and Computer Science Department at University of Michigan (U of M) under the guidance of Prof. Scott Mahlke. Before coming to U of M, he received B.S. from Pohang University of Science and Technology (POSTECH).